Beyond Capping: Reduce z13 MLC with Processor Cache Optimization
Project and Program:
MVS,
MVS Performance
Tags:
Proceedings,
2017,
SHARE San Jose 2017
One of the dominant themes of the z13 processor announcements is that delivered capacity is increasingly dependent on effective utilization of processor cache. This session will cover everything you need to know to interpret the enlightening metrics available in the SMF 113 and RMF data, and to leverage that understanding to optimize your environment and reduce CPU consumption and MLC software expense. These concepts will be illustrated with numerous real-life case study examples.
The types of configuration changes discussed will include increasing the number of hardware CPs, LPAR topology, and maximizing the number of Vertical High CPs in the HiperDispatch configuration. This session builds upon a user experience presentation on this subject that was selected for a “SHARE Best Session” award in San Antonio last Spring.-Todd Havekost-IntelliMagic
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